The present invention relates to a semiconductor memory device and manufacturing method thereof, and more particularly to a semiconductor memory device including a cell-array region and peripheral circuit region, and a method for manufacturing the same.
Decrease in cell capacitance caused by reduced memory cell area becomes serious improves the read-out capability and decreases the soft error rate in a DRAM memory cell, and therefore plays an important role in the improvement of cell memory characteristics. Due to the increase in packing density of memory cells, unit cell area per chip has decreased, which in turn reduces the area available for the cell capacitor. Therefore, the capacitance per unit area must be increased in tandem with increase in packing density.
Recently, many research reports have been published concerning increase in cell capacitance, most of them relating to the stacked structure of the cell capacitor's storage electrode. For example, they include: the fin-structured electrode ("3-dimensional Stacked Capacitor Cell for 16M and 64M" by T. Ema et al., IEDM 1988, pp. 592-595) of Fujitsu Co., the Box Structured electrode ("A New Stacked Capacitor Cell with Thin Box Structured Storage Node" by S. Inoue et al., Extended Abstracts of the 21st Conference on Solid State Devices and Materials, 1989, pp. 141-144) and SSC (Spread-Stacked Capacitor) Cell ("A Spread-Stacked Capacitor (SSC) Cell for 64 Mbit DRAMs" by S. Inoue et al., IEDM 1989, pp. 31-34) of Toshiba Co., and the cylindrical electrode ("Novel-stacked Capacitor Cell for 64 Mbit DRAMs" by W. Wakamiya et al., VLSI Technology Symposium, 1989, pp.69-70) of Mitsubishi Co.
These techniques for manufacturing a stacked capacitor constituting a DRAM have several advantages such as simple process, resistivity against alpha particles, easy increase of cell capacitance, etc. However, they have a fatal disadvantage in that they increase the step of a cell (i.e., the difference in heights from the surface of a semiconductor substrate to the topmost layer formed thereon after completing a cell). Such increase of the step of cell makes subsequent metallization processes difficult, particularly, on the border region between a cell array region and a peripheral circuit region.
FIG. 1 is a sectional view showing a conventional semiconductor memory device including a cell array region, a peripheral circuit region, and a border region between the cell array region and peripheral circuit region. The cell array region includes transistors which respectively consist of a source regions 14, drain regions 16, and gate electrodes 18, an insulating layer 20 for isolating the above gate electrode 18 from other conductive layers, a planarization layer 26, bit lines 24 in contact with each drain region 16, capacitors C1, C2 and C3. Each capacitor consists of a storage electrode 100, a dielectric film 110 and a plate electrode 120, with a portion thereof in contact with the source region of respective transistors. The peripheral circuit region includes several sense amplifiers as well as other elements constituting the peripheral circuitry shown here as one MOS transistor formed by source region 14, drain region 16 and gate electrode 18.
Among the above-described methods for easily increasing cell capacitance, the primary method employed is that for forming a cylindrical electrode. In the cylindrical capacitor, the outer surface as well as the inner surface are utilized as effective capacitor region for increasing cell capacitance. Accordingly, in order to increase the obtainable capacitance per unit area, the height of the cylinder is increased. However, referring to the sectional view of FIG. 1, it can be noted that the higher the cylinder (forming storage electrode 100) increases to obtain greater capacitance, the greater the step between the cell array region and peripheral region becomes. An increased step between the cell array region and peripheral circuit region causes several problems during subsequent metallization processes for forming a conductive layer 60; major problems among these are damage to the conductive layer pattern due to a notching phenomenon, the occurrence of stringers at the stepped corner, and the potential for shorts in the conductive layer (see circled portion A in FIG. 1).